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preliminary datasheet publication release date: july 2003 - 1 - revision 1.0 WMS7100 / 7101 non-volatile digital potentiometers with up/down (3-wire) interface, 10kohm, 50kohm, 100kohm resistance 256 taps without / with output buffer
WMS7100 / 7101 - 2 - 1. general description the WMS7100/7101 is a single channel 256-tap non-volat ile linear digital potentiometer available in 10k ? , 50k ? and 100k ? resistance. the device consists of up /down serial interface, tap register, decoder, resistor array, wiper switc hes, nv memory and control logics. the WMS7100 device can be configured as a two-terminal variable resistor or a three-terminal voltage divider without an output buffer, but the wms7101 device, which has a built-in output buffer, can only be configured as a three-terminal voltage divider. both devices can be used in a wide variety of applications. the output of the potentiometer is determined by its wiper position, which varies linearly between its end terminals, r a /v a and r b /v b . the wiper position, r w /v w, is controlled by up/down serial interface ( cs , inc and u/ d ) through the tap register (tr). in addition, the wiper position can also be stored into a non-volatile memory location (nvm em0), which is then automatically recalled upon power up. 2. features ? drop-in replacement for many popular parts ? single linear-taper channel ? 256 taps ? 10k, 50k and 100k end-to-end resistance ? v ss to v dd terminal voltages ? automatic recall of wiper position when power-on ? potentiometer control through up/down (3-wire) serial interface ? endurance 100,000 cycles ? data retention 100 years ? package options: - 8-pin pdip, soic or msop ? industrial temperature range: -40 to 85c ? single supply operation : 2.7v to 5.5v
WMS7100 / 7101 publication release date: july 2003 - 3 - revision 1.0 up/down serial interface tap register decode r nvmem0 nv memory nv memory control cs v ss v dd v a v b v w inc u/d 3. block diagram figure 1 ? WMS7100 block diag ram (rheostat/divider mode) figure 2 ? wms7101 block diagram (divider mode) up/down serial interface tap register decoder nvmem0 nv memory nv memory control cs v ss v dd r a /v a inc u /d r w /v w r b /v b
WMS7100 / 7101 - 4 - 4. table of contents 1. general d escription......................................................................................................... ......... 2 2. features .................................................................................................................... ..................... 2 3. block diagram............................................................................................................... ................ 3 4. table of cont ents ........................................................................................................... ........... 4 5. pin conf igurati on ........................................................................................................... ............ 5 6. pin des cription ............................................................................................................. ................ 6 7. functional descript ion...................................................................................................... ...... 7 7.1. rheostat and divider operations ........................................................................................... 7 7.1.1. rheostat configur ation .................................................................................................. ........ 7 7.1.2. divider configur ation................................................................................................... ........... 7 7.2. non-volatile memory (nvmem0) ........................................................................................... 7 7.3. serial data interface ................................................................................................................. 8 7.4. operation overview .................................................................................................................. 8 8. timing diagrams............................................................................................................. ............... 9 9. absolute maximum ratings & operating co nditions .................................................. 11 10. electrical cha racteris tics ............................................................................................... 12 10.1 test circuits ............................................................................................................................ 14 11. typical applic ation ci rcuits............................................................................................... 15 11.1. layout considerations .......................................................................................................... 17 12. package drawings and dimens ions.................................................................................. 18 13. ordering informat ion....................................................................................................... .... 21 14. version history ............................................................................................................ ........... 22
WMS7100 / 7101 publication release date: july 2003 - 5 - revision 1.0 5. pin configuration 1 v ss 1 2 3 4 5 6 7 8 2 3 45 6 7 8 1 2 3 45 6 7 8 inc v dd u/d r a /v a cs r b /v b r w /v w v ss r w /v w r w /v w 8-msop 8-soic 8-pdip inc u/d r a /v a v dd cs r b /v b v ss inc u/d r a /v a v dd cs r b /v b
WMS7100 / 7101 - 6 - 6. pin description table 1 ? pin description pin name description cs chip select: when cs is low, the device is enabled. when cs is high, the part is deselected and is in standby mode u/ d up/down control: high state enables the wiper to move towards the r a / v a terminal, while low state implies the wiper moves towards the r b / v b terminal inc increment control: when cs is low, a high-low transition on inc will move the wiper one increment either up or down based on the u/ d input r a /v a high terminal of the device r b /v b low terminal of the device r w /v w wiper terminal: output of the resistor array is determined by the inc , u/ d and cs inputs v ss ground pin, logic ground reference v dd power supply notes: the terminology of high and low term inals above references to the relative position of the terminal with respect to the wiper moving direction and not the voltage potential of the terminal.
WMS7100 / 7101 publication release date: july 2003 - 7 - revision 1.0 7. functional description 7.1. r heostat a nd d ivider o perations the WMS7100 device can operate as either a two-term inal variable resistor or a three-terminal voltage divider without an output buffer. however, the wms7101 can only operate in a three-terminal voltage divider with an output buffer. 7.1.1. rheostat configuration in the rheostat mode, the WMS7100 can be configured as a two-terminal resistive element, where one terminal is connected to one end of the resistor (r a or r b ) and the other terminal is the wiper (r w ). the moving direction of the wiper depends upon the setting of u/ d control signal. when the u/ d is set to up, then the wiper moves towards r a . conversely, when the u/ d is set to down, then the wiper moves towards r b . the wiper movement to either dire ction is controlled by toggling the inc signal from high to low. this configuration controls the resistance between the wiper and eit her end. the wiper resistance can be adjusted by either changing the wiper position or loading a stored wiper position value from nvmem0 upon power up. 7.1.2. divider configuration additionally, the WMS7100 can also be configured as a voltage divider. with an input voltage applied to one end (usually v a ), the ground is connected to the other end (usually v b ). these input voltages cannot exceed the v dd level or go below the v ss level. the voltage on the wiper, v w , is proportional to the wiper position with respect to the voltage difference between v a and v b . the moving direction of the wiper depends upon the setting of the u/ d control signal. when the u/ d is set to up, then the wiper moves towards v a . conversely, when the u/ d is set to down, then the wiper moves towards v b . the wiper movement to either dire ction is controlled by toggling the inc signal from high to low. nevertheless, the wms7101 can only be configured as a voltage divider and operate similarly as the WMS7100 device. the only difference is wms7101 has an output buffer, but WMS7100 doesn?t have. besides, the resistance cannot be directly measured in this configuration. 7.2. n on -v olatile m emory (nvmem0) the WMS7100/7101 has one nvmem0 location available fo r storing the current wiper position via the up/down serial interface. this stored value is aut omatically recalled and loaded into the tap register upon power up.
WMS7100 / 7101 - 8 - 7.3. s erial d ata i nterface the WMS7100/7101 device has a 3-wire up/d own serial interface consisting of cs , inc and u/ d control signals. the key features of this interface include: ? enabling the device ? determining the moving direction of the wiper ? increment/decrement operation on the wiper ? non-volatile storage of the present wiper posit ion into the nvmem0 for automatic recall at power up ? entering into the standby mode 7.4. o peration o verview the wiper position can be changed eit her up or down by operating the cs , u/ d and inc control signals. when cs is low, the device is selected and t he wiper can be moved by toggling the inc . as a result, the wiper moves up when u/ d is high and moves down when u/ d is low. the status of the u/ d can be changed even though the cs remains low. this allows the system to enable the device and then move the wiper position either up or down until the desired position is reached. when the wiper is already at the lowest positi on, further down operation won?t change the wiper position. similarly, when the wiper is at the hi ghest position, further up operation won?t change the wiper position too. the current wiper position can be automatica lly stored into the nvmem0 each time the cs goes from low to high while the inc remains high. adversely, if the inc is low when the cs goes high, the wiper position cannot be stored. meanwh ile, the nvmem0 content is automatically loaded into the wiper during power on. when the cs is held high, the device enters into standby mode and the wiper position cannot be changed. changing the cs to low exits the standby m ode and enables the device again. the operating modes of up/down interfac e are summarized in the table below: cs u/ d inc operation low high high to low move wiper toward r a /v a low low high to low move wiper toward r b /v b low to high x high store current wiper position low to high x low no store, return to standby high x x standby note: x means don?t care
WMS7100 / 7101 publication release date: july 2003 - 9 - revision 1.0 8. timing diagrams conditions: v dd = +2.7v to 5.5v, v a = v dd , v b = 0v, t = 25 c figure 3 ?WMS7100/1 timing diagram note: [1] this only applies to the power-up sequence. [2] mi in the ac timing diagram (figure 3) refers to the mi nimum incremental change in the wiper output due to a change in the wiper position. u /d cs inc t i l t i h t c yc v w mi [ 2 ] 90% 90% 10% (store) t cph t i w t pud [ 1 ] t ci t ci t di t id t f t r
WMS7100 / 7101 - 10 - table 10 ? timing parameters parameters symbol min. max. units cs to inc setup t ci 100 ns u/ d to inc setup t di 50 ns u/ d to inc hold t id 100 ns inc low period t il 250 ns inc high period t ih 250 ns inc inactive to cs inactive t ic 1 s cs deselect time (no store) t cph 100 ns cs deselect time (store) t cph 15 (2.7v) 30 (5.5v) ms inc to wiper change t iw 5 s inc cycle time t cyc 1 s inc input rise and fall time t r , t f 500 s power-up delay t pud 1 ms v cc power-up rate t r v cc 0.2 (13ms 0-2.7v) 50 (54 s 0-2.7v) v/ms
WMS7100 / 7101 publication release date: july 2003 - 11 - revision 1.0 9. absolute maximum ratings & operating conditions table 11 ? absolute maximum ratings (packaged parts) [1] conditions values junction temperature 150oc storage temperature -65o to +150oc voltage applied to any pad (v ss ? 0.3v) to (v dd + 0.3v) lead temperature (soldering ? 10 seconds) 300oc v ss ? v dd -0.3 to 7.0v table 12 ? operating conditions (packaged parts) conditions values industrial operating temperature -40oc to +85oc supply voltage (v dd ) +2.7v to +5.5v ground voltage (v ss ) 0v [1] stresses above those listed may cause permanent damage to the device. exposure to the absolute maximum ratings may affect device performance and reliability. functional operation is not im plied at these conditions.
WMS7100 / 7101 - 12 - 10. electrical characteristics table 12 ? electrical characteristics (packaged parts) parameters symbol min. typ. max. units conditionds [5] rheostat mode nominal resistance r -20 +20 % t=25oc, wiper open different non linearity [2] r-dnl -1 0.4 +1 lsb [6] integral non linearity [2] r-inl -1 0.6 +1 lsb [6] tempo [1] ? r ab / ? t 300 ppm/ c wiper resistance [2] r w 50 ? v dd =5v, i=v dd /r total [7] 80 ? v dd =2.7v, i=v dd /r total [7] wiper current i w -1 1 ma divider mode resolution n 8 bits different non linearity [2] dnl -1 0.4 +1 lsb integral non linearity [2] inl -1 0.2 +1 lsb temperature coefficient [1] ? w / ? t +20 ppm/ c wiper at center full scale error v fse -1 0 lsb wiper at highest position zero scale error v zse 0 1 lsb wiper at lowest position resistor terminal voltage range v a , v b , v w v ss v dd v terminal capacitance [1] c a , c b 30 pf wiper capacitance [1] 30 pf dynamic characteristics [1] bw 10k 1.5 mhz v dd =5v, b =vss bandwidth ?3db bw 50k 300 khz wiper at center bw 100k 200 khz analog output (buffer enables) amp output current i out 3 ma v o =1/2 scale amp output resistance rout 1 10 ? i l = 100ua total harmonic distortion [1] thd 0.08 % a =2.5v, v dd =5v, f=1khz, v in =1v rms digital inputs/outputs input high voltage v ih 0.7xv dd v input low voltage v il 0.3xv dd v output low voltage v ol 0.4 v i ol =2ma
WMS7100 / 7101 publication release date: july 2003 - 13 - revision 1.0 table 12 ? electrical characteristics (packaged parts) ? cont?d parameters symbol min. typ. max. units conditionds [5] input leakage current i li -1 +1 ua cs =v dd ,vin=vss ~ v dd output leakage current i lo -1 +1 ua cs =v dd ,vin=v ss ~ v dd input capacitance [1] c in 25 pf v dd =5v, fc = 1mhz output capacitance [1] c out 25 pf v dd =5v, fc = 1mhz power requirements operating voltage v dd 2.7 5.5 v operating current i ddr , i ddw 1 2 ma all operations i sa [3] 0.5 1 ma buffer = on cs = high, no load standby current i sb [4] 0.1 1 ua buffer = off cs = high, no load power supply rejection ratio psrr 1 lsb/v v dd =5v 10%, wiper at center notes: [1] not subject to production test. [2] lsb = (r a /v a ? r b /v b ) / (t - 1); dnl = (v i - v i+1 ) / lsb + 1 (if increment) or = (v i - v i+1 ) / lsb - 1 (if decrement); inl = (v i - i*lsb) / lsb; where i = [0, (t -1)] and t = # of taps of the device. [3] wms7101 only. [4] WMS7100 only. [5] conditions: v cc = 2.7 to 5.5v, t = 25oc and timing m easured at 50% level, unless stated. [6] only guarantee by design. [7] r total = end-to-end resistance.
WMS7100 / 7101 - 14 - 10.1 t est c ircuits figure 4 ? test circuits potentiometer divider nonlinearit y error test circuit ( inl, dnl ) *assume infinite in p ut im p edance v+ v ms * v+ = v dd 1lsb = v + / 255 wms71xx v a v b v w resistor p osition nonlinearit y error test circuit (rheostat operation: r-inl, r-dnl) *assume infinite in p ut im p edance no connection v ms * wms71xx w r a r b r w i w wms71xx wi p er resistance test circuit *assume infinite in p ut im p edance v ms * wms71xx v a v b v w i w i w = v dd /r total r w = v ms /i w power supply sensitivity te st circuit (pss, psrr) *assume infinite in p ut im p edance + v v a v b v w v ms * psrr ( db ) = 20log ( ) ? v ms ? v dd pss ( %/% ) = ? v ms ? v dd wms71xx v a v b v w v in ~ +5v 2.5v dc offset v out ca p acitance test circuit v a v b wms71xx v w v in ~ +5v 2.5v dc v out offset gnd gain vs . fre q uenc y test circuit v a v a = v dd v + = v dd 10%
WMS7100 / 7101 publication release date: july 2003 - 15 - revision 1.0 11. typical application circuits vin v out = - v in a b r r r a = , r b = r ab = total resistance of potentiometer w = wiper setting for wms71xx figure 5 ? programmable inverting gain amplifier using the WMS7100/7101 v out = v in (1+ a b r r ) r a = , r b = r ab = total resistance of potentiometer w = wiper setting for wms71xx figure 6 ? programmable non-inverting gain amplifier using the WMS7100/7101 op a mp _ v out wms71xx + op a mp v in v out wms71xx _ r a r b r a r b + r ab (256-w) 256 256 r ab *w r ab (256-w) 256 256 r ab *w
WMS7100 / 7101 - 16 - figure 7 ? wms7101 trimmi ng voltage reference figure 8 ? wms7101 rf amp control filter l1 choke wms71xx winpot cs\ u/d\ inc\ v ss r a /v a r w /v w r b /v b v dd rf input rf out q1 rf power amp c1 0.1uf c2 cs\ inc\ u/d\ v refh wms71xx v+ gnd v ref = 5.0v 0v 5v vout
WMS7100 / 7101 publication release date: july 2003 - 17 - revision 1.0 11.1. l ayout c onsiderations use a 0.1 f bypass capacitor as close as possible to the v dd pin. this is recommended for best performance. often this can be done by placing the surface mount capacitor on the bottom side of the pc board, directly between the v dd and v ss pins. care should be taken to separate the analog and digital traces. sensitive traces should not run under the device or close to the bypass capacitors. a dedicated plane for analog ground helps in reduc ing ground noise for sensitive analog signals. cap v dd cs r b /v b r w /v w inc u/d r a /v a v ss analog signal lines digital control lines analog signal line digital control line figure 9 ? WMS7100/7101 layout
WMS7100 / 7101 - 18 - 12. package drawings and dimensions e 1 8 5 4 control demensions are in milmeters . e figure 10: 8l 150mil soic
WMS7100 / 7101 publication release date: july 2003 - 19 - revision 1.0 1.63 1.47 0.064 0.058 symbol min nom max max nom min dim ension in inch d im ension in m m a b c d e a l s a a 1 2 e 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.375 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.255 0.250 0.245 6.48 6.35 6.22 9.53 7.62 7.37 7.87 0.300 0.290 0.310 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 0.360 0.380 9.14 9.65 0 15 0.045 1.14 0.355 0.335 8.51 9.02 15 0 seating plane e a 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 8 5 1 4 figure 11: 8l 300mil pdip
WMS7100 / 7101 - 20 - figure 12: 8l 3mm msop
WMS7100 / 7101 publication release date: july 2003 - 21 - revision 1.0 13. ordering information winbond?s winpot part number description: output buffer end-to-end resistance soic pdip msop 10k WMS7100 010s WMS7100 010p WMS7100 010m 50k WMS7100 050s WMS7100 050p WMS7100 050m no 100k WMS7100 100s WMS7100 100p WMS7100 100m 10k wms7101 010s wms7101 010p wms7101 010m 50k wms7101 050s wms7101 050p wms7101 050m yes 100k wms7101 100s wms7101 100p wms7101 100m notes: part number with white background: av ailable for sampling and mass production. part numbers with shaded background: call factory for availability. for the latest product information, access winbond?s worldwide website at http://www.wi nbond-usa.com t b rrr p winbond winpot products w/ up-down interface number of taps: 0 = 256 wms71 for up/down interface: 0 : no buffer 1 : with buffer end-to-end resistance: 010: 10kohm 050: 50kohm 100: 100kohm package: s: soic p: pdip m: msop
WMS7100 / 7101 - 22 - 14. version history version date description 1.0 july 2003 initial issue headquarters winbond electronics corporati on america winbond electronics (shanghai) ltd. no. 4, creation rd. iii 2727 north first street, san jose, 27f, 299 yan an w. rd. shanghai, science-based industrial park, ca 95134, u.s.a. 200336 china hsinchu, taiwan tel: 1-408-9436666 tel: 86-21-62365999 tel: 886-3-5770066 fax: 1-408-5441797 fax: 86-21-62356998 fax: 886-3-5665577 http:// www.wi nbond-usa.com/ http://www. winbond.com.tw/ taipei office winbond electronics corporat ion japan winbond electronics (h.k.) ltd. 9f, no. 480, pueiguang rd. 7f daini-ueno bldg. 3-7-18 unit 9-15, 22f, millennium city, neihu district shinyokohama kohokuku, no. 378 kwun tong rd., taipei, 114 taiwan yokohama, 222-0033 kowloon, hong kong tel: 886-2-81777168 tel: 81-45-4781881 tel: 852-27513100 fax: 886-2-87153579 fax: 81-45-4781800 fax: 852-27552064 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. this product incorporates superflash ? technology licensed from sst. the contents of this document are provided only as a guide for the applications of winbond products. winbond makes no representation or warranties with respect to the accuracy o r completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and produc t descriptions at any time wit hout notice. no license, whethe r express or implied, to any intelle ctual property or other right of winbond or others is granted by this publication. except as set forth in wi nbond's standard terms and conditions of sale, winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infr ingement of any intellectual property. winbond products are not designed, intended, author ized or warranted for use as components in systems or equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportati on instruments, traffi c signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further, winbond products are not intended for app lications wherein failure of winbond products could result or lead to a situation wherei n personal injury, death or severe property o r environmental in j ur y could occur.

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